View HSD8M32F4V-10_632853.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HANBit
HSD8M32F4V/VA
Synchronous DRAM Module 32Mbyte ( 8M x 32-Bit ) SMM based on 8Mx8, 4Banks, 4K Ref., 3.3V Part No. HSD8M32F4V/VA
GENERAL DESCRIPTION
The HSD8M32F4V/VA is a 8M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages is mounted on a 120-pin, single-sided, FR-4-printed circuit board., Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD8M32F4V/VA is a SMM (Stackable Memory Module) designed and is intended for mounting into two 60pin connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
* Part Identification
PIN ASSIGNMENT
60-PIN P1 Connector 60-PIN P2 Connector PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol Vss DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Vss DQM2 DQM3 NC BA0 BA1 A10/AP A0 A1 A2 A3 Vss PIN 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol Vcc DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 Vcc DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Vcc DQM6 DQM7 NC A11 A9 A8 A7 A6 A5 A4 Vcc
HSD8M32F4V : Height from bottom to top 11.3mm HSD8M32F4VA : Height from bottom to top 7.3mm * Burst mode operation * Auto & self refresh capability (4096 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * 120pin SMM type FR4-PCB design * The used device is 4Mx8bit x4Banks SDRAM * Pin assignment is compatible with - HSD16M64F8V/VA - HSD32M64F8V/VA - HSD8M64F8V/VA
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Symbol Vcc DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 Vcc DQM4 DQM5 NC CKE0 CKE1 Vcc NC NC /CE2 NC Vcc
PIN 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Symbol Vss DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Vss DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Vss DQM0 DQM1 /WE CLK0 CLK1 Vss /CAS /RAS /CE0 NC Vss
Stackable Memory Module TOP VIEW
URL:www.hbe.co.kr REV.1.0 (August.2002)
1
HANBit Electronics Co.,Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
DQ0-31
HSD8M32F4V/VA
CKE0 /CAS /RAS /CE0
CKE CAS RAS CE WE A0-A11
CLK
CLK0
U1
DQ0-7 DQM0 BA0-1 DQM0
CKE CAS RAS CE WE A0-A11
CLK
CLK0
U5
DQ8-15 DQM0 BA0-1 DQM1
CKE CAS RAS CE WE A0-A11
CLK
CLK0
U3
DQ16-23 DQM0 BA0-1 DQM2
CKE CAS RAS CE WE A0-A11
CLK
CLK0
U7
DQ24-31 DQM0 BA0-1 DQM3
/WE A0 - A11 BA0-1
Vcc
Two 0.01uF Capacitor per each SDRAM
Vss
URL:www.hbe.co.kr REV.1.0 (August.2002)
2
HANBit Electronics Co.,Ltd.
HANBit
PIN FUNCTION DESCRIPTION
Pin CLK /CE Name System clock Chip enable Input Function
HSD8M32F4V/VA
Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge.
/CAS
Column strobe
address
Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active.
/WE
Write enable
DQM0 ~ 7
Data mask
input/output
Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
DQ0 ~ 63 VDD/VSS
Data input/output Power supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG RATING -1V to 4.6V -1V to 4.6V 4W -55oC to 150oC
Short Circuit Output Current IOS 400mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
URL:www.hbe.co.kr REV.1.0 (August.2002)
3
HANBit Electronics Co.,Ltd.
HANBit
HSD8M32F4V/VA
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4 UNIT V V V V V 1 2 IOH = -2mA IOL = 2mA 3 NOTE
Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23 C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Clock /RAS, /CAS,/WE,/CS, CKE, DQM Address DQ (DQ0 ~ DQ7) SYMBOL CCLK CIN CADD COUT MIN 2.5 2.5 2.5 4.0 MAX 1.6 20.0 20.0 26.0 UNITS pF pF pF pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70 C) PARAMETER SYMBOL TEST CONDITION Burst length = 1 Operating current (One bank active) ICC1 tRC tRC(min) IO = 0mA ICC2P CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= CKE VIH(min) Precharge standby current in non power-down mode ICC2N CS* VIH(min), tCC=10ns 60 mA 4 mA 4 mA 300 300 280 280 mA 1 VERSION UNIT -13 -12 -10 -10L NOTE
Precharge standby current in power-down mode
ICC2PS
Input signals are changed one time during 20ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
4
HANBit Electronics Co.,Ltd.
HANBit
CKE VIH(min) ICC2NS CLK VIL(max), tCC=
HSD8M32F4V/VA
28
Input signals are stable Active standby current in ICC3P ICC3PS CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= CKEVIH(min), ICC3N CS*VIH(min), tCC=10ns 120 mA 20 mA 20
power-down mode
Active standby current in non power-down mode (One bank active)
Input signals are changed one time during 20ns CKEVIH(min)
ICC3NS
CLK VIL(max),
tCC=
80
Input signals are stable IO = 0 mA Operating current (Burst mode) ICC4 Page burst 600 4Banks Activated tCCD = 2CLKs Refresh current Self refresh current ICC5 ICC6 tRC tRC(min) CKE 0.2V 880 880 4 3200 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). 840 840 mA mA mA 2 580 500 500 mA 1
AC OPERATING TEST CONDITIONS
(vcc = 3.3V 0.3V, TA = 0 to 70 C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V Ns V
URL:www.hbe.co.kr REV.1.0 (August.2002)
5
HANBit Electronics Co.,Ltd.
HANBit
HSD8M32F4V/VA
+3.3V
Vtt=1.4V
1200 DOUT 870 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA
(Fig. 1) DC output load circuit
50 DOUT Z0=50 50pF
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) VERSION PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time SYMBOL -13 tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max)
tRC(min)
UNIT -12 16 20 20 48 100 65 68 2 2 CLK + 20 ns 1 1 1 2 ea CLK CLK CLK 70 70 -10 20 20 20 50 -10L 20 20 20 50 ns ns ns ns ns ns CLK 15 20 20 45
NOTE 1 1 1 1
Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data
1 2.5
tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 -
2 2 3 4
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .
URL:www.hbe.co.kr REV.1.0 (August.2002)
6
HANBit Electronics Co.,Ltd.
HANBit
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) -13 PARAMETER CLK cycle time CAS 7.5 latency=3 tCC CAS latency=2 CLK to valid output delay CAS 5.4 latency=3 tSAC CAS latency=2 Output data hold time CAS 2.7 latency=3 tOH CAS latency=2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS 5.4 latency=3 tSHZ CAS latency=2 6 6 6 tCH tCL tSS tSH tSLZ 2.5 2.5 1.5 0.8 1 3 3 2 1 1 3 3 2 1 1 3 3 3 6 6 6 10 1000 1000 1000 8 10 SYMBOL MIN MAX MIN MAX MIN MAX -12 -10
HSD8M32F4V/VA
-10L UNIT MIN 10 1000 12 ns 1 MAX NOTE
6 ns 7 1,2
3 ns 3 3 3 2 1 1 6 ns ns ns ns ns ns 3 3 3 3 3 2 2
7
ns
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter.
URL:www.hbe.co.kr REV.1.0 (August.2002)
7
HANBit Electronics Co.,Ltd.
HANBit
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode register set Auto refresh Refresh Self refres h Auto disable Auto disable Auto disable Auto disable Burst Stop Precharg e Bank selection All banks Entry Exit Entry Exit H H H L H L H H X H L X X L H L H L L H L X H L H L L L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X V X precharge precharge H X L H L L X V precharge Entry Exit CKE n-1 H H L H CKE n X H L H X /C S L L L H L /R A S L L H X L /C A S L L H X H /W E L H H X H D Q M X X X X V BA 0,1
HSD8M32F4V/VA
A10/ AP OP code X X
A11 A9~A0
NOTE 1,2 3 3 3 3
Bank active & row addr. Read & column address precharge
Row address L Column Address H (A0 ~ A9) Column L Address (A0 ~ A9) H X L H X X 4,5 6 4 4,5 4
H
X
L
H
L
H
X
V
Write & column address
Clock suspend or active power down
Precharge down mode DQM
power
X X V X X X 7
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
URL:www.hbe.co.kr REV.1.0 (August.2002)
8
HANBit Electronics Co.,Ltd.
HANBit
TIMING DIAGRAMS
Please refer to attached timing diagram chart (II)
HSD8M32F4V/VA
PACKAGING INFORMATION
Unit : mm
HSD8M32F4V
82.68. 5.00 0.90 5.00
0.90
31
1
31
1
30.00
60
30 P2
60 P1
30
0.90 Bottom View
0.90
1.30
9.00 4.60
MAIN BOARD 7.75
Connector Configuration
- Module PCB Bottom: AMP 177986-2, 0.8mm Free Height Plugs, 60pins - Board top, Module PCB Top:AMP 5-179180-2,0.8mm Free Height Receptacles , 60pins
HSD8M32F4VA
URL:www.hbe.co.kr REV.1.0 (August.2002)
9
HANBit Electronics Co.,Ltd.
HANBit
HSD8M32F4V/VA
82.68. 5.00 0.90 5.00
0.90
31
1
31
1
30.00
60
30 P2
60 P1
30
0.90 Bottom View
0.90
1.30
5.00 4.60
MAIN BOARD 3.75
Connector Configuration
- Module PCB Bottom: AMP 177984-2, 0.8mm Free Height Plugs, 60pins - Board top, Module PCB Top : AMP 177983-2,0.8mm Free Height Receptacles , 60pins
ORDERING INFORMATION
URL:www.hbe.co.kr REV.1.0 (August.2002)
10
HANBit Electronics Co.,Ltd.
HANBit
HSD8M32F4V/VA
Part Number
Density
Org.
Package
Ref.
Vcc
Feature
MAX.frq
HSD8M32F4V-13 HSD8M32F4V-12 HSD8M32F4V-10 HSD8M32F4V-10L HSD8M32F4VA-13 HSD8M32F4VA-12 HSD8M32F4VA-10 HSD8M32F4VA-10L
32MByte 32MByte 32MByte 32MByte 32MByte 32MByte 32MByte 32MByte
8Mx 32 8Mx 32 8Mx 32 8Mx 32 8Mx 32 8Mx 32 8Mx 32 8Mx 32
120 Pin SMM 120 Pin SMM 120 Pin SMM 120 Pin SMM 120 Pin SMM 120 Pin SMM 120 Pin SMM 120 Pin SMM
4K 4K 4K 4K 4K 4K 4K 4K
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
CL=3 CL=3 CL=2 CL=3 CL=3 CL=3 CL=2 CL=3
133MHz 125MHz 100MHz 100MHz 133MHz 125MHz 100MHz 100MHz
URL:www.hbe.co.kr REV.1.0 (August.2002)
11
HANBit Electronics Co.,Ltd.

▲Up To Search▲

Price & Availability of HSD8M32F4V-10

	To Download HSD8M32F4V-10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .